Well structure in high voltage device

ABSTRACT

The present invention relates to a well structure in a high voltage device. A well structure in a high voltage device, comprising; a first well formed in a substrate, the first well having an opposite conductive type from the substrate; a second well isolated from the first well, the second well having the same conductive type as the substrate; a field stop implant region formed between the first well and the second well and spaced apart from each of the first well and the second well by a given distance, the field stop implant region having the same conductive type as the substrate; and a pick-up region overlapped on the field stop implant region, the pick-up region having the same conductive type as the field stop implant region.

BACKGROUND

[0001] 1. Field of the Invention

[0002] The present invention relates to a well structure in a highvoltage device and, more particularly, to a well structure in a highvoltage device capable of improving a well breakdown voltage (BVDSS) andpreventing charge-up and latch-up at a substrate in the high voltagedevice used in a flash memory.

[0003] 2. Discussion of Related Art

[0004] In general, the flash memory is mainly classified into an NORtype and a NAND type depending on a shape in which memory cells areconnected to bit lines. A high voltage is used in the NAND type flashmemory or the NOR type flash memory in order to perform a programoperation or an erase operation. In order for the NAND type flash memoryto perform the program operation or the erase operation, a voltage ofabout 20V is required. Further, in order for the NOR type flash memoryto perform the program operation or the erase operation, a voltage ofabout 14V is needed. In order to apply such high voltage to a cellregion, a high voltage device is located in a peripheral circuit region.

[0005] In case of the NAND type flash memory, upon the program operationand the erase operation, a high voltage of about 20V is used asdescribed above. Such a high voltage is obtained through a high voltagedevice. The high voltage device has a PMOS transistor and a nativetransistor within the N-well. As the N-well and N⁺-pickup are applied ahigh voltage, it is required that the well breakdown voltage of theN-well itself be about 30V. In other words, upon the program operationand the erase operation of the NAND type flash memory, in order for thehigh voltage device to stably apply the high voltage to the celltransistor, it is required that the well breakdown voltage of the highvoltage device be 30V or higher. Even in case of the NOR type flashmemory, it may well have a high well breakdown voltage even though itsvalue may be different from that of the NAND type flash memory.

[0006]FIG. 1 is a cross-sectional view illustrating a basic wellstructure in a conventional high voltage device. In order to have a highwell breakdown voltage, an N-well 12 is formed in a P type substrate 11and a P-well 13 spaced apart from the N-well 12 by a given distance isformed in the P type substrate 11. In case of a structure in which theN-well 12 and the P-well 13 contact each other, the well breakdownvoltage is about 18V. The high voltage device of this well structurecould not be applied to devices that require the well breakdown voltageof 18V or higher, for example, the NAND type flash memory. Therefore, incase of the NAND type flash memory, the N-well 12 is separated by adistance of 20 μm or greater from the P-well 13 when it is formed in theP type substrate 11. In more detail, in the N-well 12 within the P typesubstrate 11, a lateral diffusion becomes about 1 μm, the depletionregion is abruptly formed at a low voltage and the depletion region isnot increased at a voltage of over a given value, i.e., due to a highresistance of the P type substrate 11. For this reason, a breakdownvoltage of 40V or higher is kept at a distance of 20 μm or greater. Assuch, in case of the NAND flash memory, there occurs a problem where thehigh voltage device is formed by making the distance between the N-well12 and the P-well 13 20 μm or greater. As the density of the NAND typeflash memory recently becomes higher, it is required that the distancebetween the N-well 12 and the P-well 13 be narrowed. In order to solvethis problem, in the NAND type flash memory of 0.12 μm level, field stopimplant region 14 using boron is formed in the P type substrate 11between the N-well 12 and the P-well 13. From a simulation shown in FIG.3, however, it can be seen that the well breakdown voltage is low, about23V, when the N-well 12 and the field stop implant region 14 areconnected (0.0 μm). In FIG. 1, an unexplained reference numeral 15indicates a field oxide film.

[0007] As described above, the conventional well structure in the highvoltage device has limitations in higher-integration of the flash memoryor the semiconductor device that requires the high well breakdownvoltage.

SUMMARY OF THE INVENTION

[0008] The present invention is contrived to solve the aforementionedproblems. The present invention is directed to provide a well structurein a high voltage device capable of improving performance andreliability of the device and realizing higher-integration of thedevice, by improving a well breakdown voltage and preventing charge-upand latch-up at a substrate.

[0009] One aspect of the present invention is to provide a wellstructure in a high voltage device, a well structure in a high voltagedevice, comprising; a first well formed in a substrate, the first wellhaving an opposite conductive type from the substrate; a second wellisolated from the first well, the second well having the same conductivetype as the substrate; a field stop implant region formed between thefirst well and the second well and spaced apart from each of the firstwell and the second well by a given distance, the field stop implantregion having the same conductive type as the substrate; and a pick-upregion overlapped on the field stop implant region, the pick-up regionhaving the same conductive type as the field stop implant region.

[0010] In the aforementioned of a well structure in a high voltagedevice according to another embodiment of the present invention, thesubstrate is a P type substrate.

[0011] In the aforementioned of a well structure in a high voltagedevice according to another embodiment of the present invention, thefirst well is an N-well into which phosphorous (Ph) is implanted.

[0012] In the aforementioned of a well structure in a high voltagedevice according to another embodiment of the present invention, thesecond well is a P-well into which boron (B) is implanted.

[0013] In the aforementioned of a well structure in a high voltagedevice according to another embodiment of the present invention, thefield stop implant region is formed by implanting boron (B).

[0014] In the aforementioned of a well structure in a high voltagedevice according to another embodiment of the present invention, thespaced distance between the first well and the field stop implant regionis in the range of 0.5 μm to 1.5 μm.

[0015] In the aforementioned of a well structure in a high voltagedevice according to another embodiment of the present invention, thespaced distance between the second well and the field stop implantregion is 0.5 to 1.5 μm.

[0016] In the aforementioned of a well structure in a high voltagedevice according to another embodiment of the present invention, thepick-up region is formed by implanting boron (B) with highconcentration.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of thepresent invention will become apparent from the following description ofpreferred embodiments given in conjunction with the accompanyingdrawings, in which;

[0018]FIG. 1 is a cross-sectional view illustrating a basic wellstructure in a conventional high voltage device;

[0019]FIG. 2 is a cross-sectional view illustrating a well structure ina high voltage device according to an embodiment of the presentinvention; and

[0020]FIG. 3 illustrates a simulation result that an N-well breakdownvoltage is measured while varying the distance between a field stopimplant region and an N-well.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0021] The present invention will now be described in detail inconnection with preferred embodiments with reference to the accompanyingdrawings.

[0022]FIG. 2 is a cross-sectional view illustrating a well structure ina high voltage device according to an embodiment of the presentinvention. The proposed well structure may be applied to a NAND typeflash memory, an NOR type flash memory and all the semiconductordevices, which require a high voltage.

[0023] Referring to FIG. 2, a first well 22 is formed by implanting animpurity of a conductive type different from a substrate 21 into thesubstrate 21. A first transistor for a high voltage is contained in thefirst well 22 by means of a common process. A second well 23 is isolatedfrom the first well 22 and is formed by implanting an impurity of thesame conductive type to the substrate 21 into the substrate 21. A secondtransistor for a high voltage is contained in the second well 23 bymeans of a common process. A field stop implant region 24 is formedbetween the first well 22 and the second well 23 by implanting animpurity of the same conductive type to the substrate 21 into thesubstrate 21. At this time, the field stop implant region 24 is spacedapart from each of the first well 22 and the second well 23 by a givendistance. A pick-up region 26 has the same conductive type to the fieldstop implant region 24 and is overlapped on the field stop implantregion 24.

[0024] In a high voltage device, the substrate 21 is mainly a P typesubstrate. Therefore, the first well 22 becomes an N well by implantingthe impurity of the conductive type different from the substrate 21, forexample, phosphorous (Ph). Further, the second well 23 becomes a P wellby implanting the impurity of the same conductive type to the substrate21, for example, boron (B).

[0025] In the above, the field stop implant region 24 may be formed byimplanting the impurity of the same conductive type to the substrate 21,for example boron (B) before a deposition process of HDP oxide forforming a field oxide film 25 after an ISO etch process in the processof manufacturing the flash memory, or may be formed by implanting boron(B) through additional process other than the process of manufacturingthe flash memory.

[0026] The field stop implant region 24 is spaced apart from the firstwell 22 being the N-well by a given distance. This allows phosphorous(Ph31) of the first well 22 and boron (B) of the field stop implantregion 24 not to directly meet, thus improving the well breakdownvoltage. FIG. 3 illustrates a simulation result that the N-wellbreakdown voltage is measured while varying the distance between thefield stop implant region and the N-well in the NAND type flash memoryof 0.12 μm level. It can be seen from FIG. 3 that the well breakdownvoltage is about 23V when the distance between the field stop implantregion 24 and the first well 22 is 0.0 μm. Further, it can be seen that,when the distance is 0.5 μm or greater, the N-well breakdown voltage ofabout 30V or higher can be obtained. Accordingly, in order to improvethe well breakdown voltage of the high voltage device, the field stopimplant region 24 is formed between the first well 22 and the secondwell 23, wherein the distance between the first well 22 and the fieldstop implant region 24 is spaced apart 0.5 μm or greater, preferably 0.5to 1.5 μm.

[0027] Further, the field stop implant region 24 is spaced apart fromthe second well 23 being the P-well by a given distance. This considerscharacteristics of the NMOS transistor formed in the second well 23being the P-well. In the concrete, this is for reducing a body factoreffect. The spaced distance needs not to be limited but may be set 0.5μm or greater, preferably 0.5 to 1.5 μm.

[0028] The pick-up region 26 is formed by implanting the impurity of thesame conductive type to the field stop implant region 24, for example,boron (B) with a high concentration. This is for preventing charge-upand latch-up at the P type substrate 21. In other words, as theresistance of the P type substrate 21 is high, charges may locallygather within the P type substrate 21. For this reason, a latch-up mayoccur and erroneous function may be caused. In order to prevent them,the pick-up region 26 is formed using the same conductive type impurityto the field stop implant region 24.

[0029] According to the present invention described above, the presentinvention can improve performance and reliability of a device andrealize higher-integration of the device, by improving a well breakdownvoltage and preventing charge-up and latch-up at a substrate.

[0030] Although the present invention has been described in connectionwith the embodiment of the present invention illustrated in theaccompanying drawings, it is not limited thereto. It will be apparent tothose skilled in the art that various substitutions, modifications andchanges may be made thereto without departing from the scope and spiritof the invention.

What is claimed is:
 1. A well structure in a high voltage device,comprising; a first well formed in a substrate, the first well having anopposite conductive type from the substrate; a second well isolated fromthe first well, the second well having the same conductive type as thesubstrate; a field stop implant region formed between the first well andthe second well and spaced apart from each of the first well and thesecond well by a given distance, the field stop implant region havingthe same conductive type as the substrate; and a pick-up regionoverlapped on the field stop implant region, the pick-up region havingthe same conductive type as the field stop implant region.
 2. The wellstructure as claimed in claim 1, wherein the substrate is a P typesubstrate.
 3. The well structure as claimed in claim 1, wherein thefirst well is an N-well into which phosphorous (Ph) is implanted.
 4. Thewell structure as claimed in claim 1, wherein the second well is aP-well into which boron (B) is implanted.
 5. The well structure asclaimed in claim 1, wherein the field stop implant region is formed byimplanting boron (B).
 6. The well structure as claimed in claim 1,wherein the spaced distance between the first well and the field stopimplant region is in the range of 0.5 μm to 1.5 μm.
 7. The wellstructure as claimed in claim 1, wherein the spaced distance between thesecond well and the field stop implant region is 0.5 to 1.5 μm.
 8. Thewell structure as claimed in claim 1, wherein the pick-up region isformed by implanting boron (B) with high concentration.